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2D MEANDER Framework
 
An open-source framework for architecture-level exploration and application mapping onto 2D FPGA devices
It is the first complete academic framework starting from HDL up to configuration bitstream generation
Supports exploration and quantification of alternative reconfigurable architectures
It is modular
It is part from the AMDREL Project
It is also available through a web-based Graphical User Interface (GUI)
2D MEANDER Framework is provided upon email request
Try the on-line execution of the 2D MEANDER Framework
 
   
3D MEANDER Framework
An open-source framework for architecture-level exploration and application mapping onto 3D FPGA devices
It is the first complete academic framework starting from HDL up to configuration bitstream generation
Supports exploration and quantification of alternative reconfigurable architectures
It can handle multiple bonding technologies (i.e., TSV, wirebonding, F2F, or any combination among them)
It supports numerous stacking technologies (i.e., PiP, PoP, Wafer-on-Wafer, Die-on-Wafer)
It is modular
It is also available through a web-based Graphical User Interface (GUI)
3D MEANDER Framework is provided upon email request
 
 
3D ASIC Framework
An framework for architecture-level exploration and application mapping onto 3D ASIC devices
It deals with application floor-planning onto 3D ASIC devices
It can handle multiple bonding technologies (i.e., TSV, wirebonding, F2F, or any combination among them)
It supports numerous stacking technologies (i.e., PiP, PoP, Wafer-on-Wafer, Die-on-Wafer)
It co-operates with Cadence SoC Encounter
3D ASIC Framework is provided upon email request
 
 
3DPart Tool
HYPERGRAPH PARTITIONING, PARTITIONING TO LAYER ASSIGNMENT AND LAYER ORDERING
Supports application partitioning to N subsections and assign them to the M layers of the 3D chip
Supports flexible (designer defined) cost functions
Supports multiple connections types (i.e., buses, point-to-point, network-on-chip, or any combination)
Rather than providing the optimal solution, it also gives all the Pareto solutions that trade-off the design parameters
Co-operates with Cadence SoC Encounter
3DPart Tool is provided upon email request
 
 
Power-aware Placement & Routing Tool
Given a certain FPGA device with specific power budget, find an appropriate application mapping which:
Re-distributes the power budget over the whole FPGA device into one more "balanced" way
Reduces the number and amplitude of the power consumption peaks and hotspots
Without impact on maximum device operation frequency and total power/energy consumption
It can also be used as a power and temperature management strategy
Power-aware Placement & Routing Tool is provided upon email request
 
 
FAULT-FREE: A Framework for enabling conventional reconfigurable architectures to perform with fault-tolerant features
Enables the fault detection in reconfigurable architectures, even if the devices do not support such feature
It can be applied selectively on specific regions of the device
It supports three candidate techniques for error detection
The designer does not need to make manually any modifications to the input HDL file
Fault-Free Framework is provided upon email request
 
 
NAROUTO: Development of a design framework for Power/Energy consumption estimation in heterogeneous FPGA architectures
Enables the architecture-level exploration of FPGAs with numerous embedded IP cores
It provides power, delay and area for the application mapped onto such an FPGA
It is based on open-source tools
Among others, it supports designs from Altera QUIP
NAROUTO Framework is provided upon email request
 
 
FLEX-NoC: A Framework for bulding reusable NoC interconenction architecture at RTL
Supports a high-level topology exploration for retrieving the specifications of NoC network
The results from exploration guides an automatic tool for generation a reusable NoC interconnection architecture at RTL
The retrieved NoC is customazable in terms of routing algorithm (XY, LUT-based, ...), number of router, selected topology (regular/irregular), buffer sizes, etc
It was tested for Xilinx/Altera FPGAs, as well as for SoC (through Cadence Encounter) @ 45nm
FLEX-NoC Framework is provided upon email request
 
 
MULTI-VDD: A tool framework that supports architecture-level exploration (2D/3D) with multiple supply voltages
A high-level exploration tool for NoC-based Architectures
Routers work under multiple Vdds in order to balance delay and energy consumption
The Vdd values can be tuned dynamically
   

2D MEANDER Framework is provided upon email request
 
 
Thermal-Aware Exploration of ASIC Designs
Architecture optimization regarding thermal aware exploration by exploiting selective replication of specific architectural blocks.
Elimination of thermal hotspots at SoCs.
Alleviation to the temperature gradients.
Rather than providing only one architectural solution, our tool retrieves a number of Pareto architectural solutions, each of which trades-off different design constraints/criteria.

Thermal-aware Framework is provided upon email request
 
 

Last update: 15 November 2017

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