A Framework for Rapid System-Level Synthesis Targeting to Reconfigurable Platforms: A Computer Vision Case Study
D. Diamantopoulos, I. Galanis, K. Siozios, G. Economakos and D.Soudris
Workshop on Reconfigurable Computing (WRC), Jan. 2015, Amsterdam, Netherlands.
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Reducing time-to-market while improving product quality is a big challenge for system architects of recent multi-million gate System-on-Chips (SoCs). From the software perspective, recent electronics market is governed by the development of hardware-dependent software, i.e. multiple layers of software ready to run optimal on various heterogeneous computing platforms from different application domains, such as automotive, consumer and wireless applications. From the hardware perspective there is continuous market trend in configurable systems, so that part of their functionality can be re-programmed to adapt the client's requirements, i.e. Software Defined Radios (SDRs). In this paper we present a rapid system-level development flow that offers a concurrent fast hardware/software system-level design by enabling a) to start developing, testing and validating the embedded software substantially earlier than it has been possible in the past and b) fast flexible hardware design based on High Level Synthesis (HLS) techniques so that the under-development HW prototype is evaluated and tested in the entire development time. We evaluated our design flow with a computer vision algorithm, i.e. Harris corner detection, and we managed to decrease the development time by almost 64x by pruning the HW design space by 34x, while maintaining designs that trade-off high Quality-of-Report (QoR) on the Pareto frontier.

Last Update: 09 October 2016