A Genetic Algorithm based Partitioning for 3-D Reconfigurable Architectures

K. Maragos, K. Siozios and D. Soudris
Workshop on Reconfigurable Computing (WRC), Jan. 2015, Amsterdam, Netherlands.

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The interconnection structures in FPGA devices increasingly contribute more to the delay, power consumption and area overhead. The demand for even higher clock frequencies makes this problem even more important. Three-dimensional (3-D) chip stacking is touted as the silver bullet technology that can keep Moore’s momentum and fuel the next wave of consumer electronics products. However, the benefits of such an integration technology have not been sufficiently explored yet. In this paper, we introduce a novel partitioning scheme based on genetic algorithm targeting 3-D FPGA platforms. Experimental results prove the efficiency of our solution for a wide range of applications, since we achieve to perform application mapping onto devices consisted of fewer TSVs (on average 7.4% fewer TSVs) as compared to existing state-of-the-art solutions. Furthermore, we achieve significant smaller total wirelength (on average 12.8%) for comparable operation frequency which leads to mentionable power/energy savings.

Last Update: 09 October 2016