On Supporting Efficient Implementation of Communication-Intensive Applications onto 3D FPGAs
H. Sidiropoulos, K. Siozios and D. Soudris
Workshop on Reconfigurable Computing (WRC), Jan. 2012, Paris, France.
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The interconnection structures in FPGA devices increasingly contribute more to the delay, power consumption and area overhead. The demand for even higher clock frequencies makes this problem even more important. Three-dimensional (3-D) chip stacking is touted as the silver bullet technology that can keep Moore’s momentum and fuel the next wave of consumer electronics products. However, the benefits of such an integration technology have not been sufficiently explored yet. In this paper, we introduce a novel 3-D architecture, as well as the software supporting tools for exploring and evaluating application mapping onto 3-D FPGAs, where logic and I/O resources are assigned to different layers. Since the introduced framework is capable of providing sufficient I/O communication, it is suitable for communication intensive applications. Experimental results shown that such a 3-D architecture with 2 layers achieves delay reduction, as compared to conventional 2-D FPGAs up to 87% without any overhead in power dissipation.

Last Update: 09 October 2016