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A Methodology and Tool Framework for Supporting Rapid Exploration of Memory Hierarchies in FPGAs
 
H. Sidiropoulos, K. Siozios and D. Soudris
Workshop on Reconfigurable Computing (WRC), pp. 75-84, Jan. 2011, Heraklion, Greece.
 
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Abstract:
This paper introduces a novel methodology for enabling rapid exploration of memory hierarchies onto FPGA devices. The methodology is software supported by a new open-source tool framework, named NAROUTO. Among others, the proposed framework enables critical tasks during architecture's design, such as memory hierarchy and floor-planning. Furthermore, NAROUTO framework is the only available solution for power/energy evaluation of different memory organizations. Experimental results shown that NAROUTO framework leads to significant area, power (about 82%) and performance (about 46%) improvements, as compared to existing solutions.

Last Update: 09 October 2016