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Fault-Free: A Framework for Supporting Fault Tolerance in FPGAs
 
K. Siozios, D. Soudris and D. Pnevmatikatos
Workshop on Reconfigurable Computing (WRC), Jan. 2010, Pisa, Italy.
 
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Abstract:
In this paper we propose a novel methodology for supporting application mapping onto FPGAs with fault tolerance even if this feature is not supported by the target platform. For the purposes of this paper we incorporate three techniques for error correction. The introduced fault tolerance can be implemented either as a hardware modification, or through annotating the application’s HDL. Also, we show that the existing approaches for fault tolerance result to hardware wastage, since there is no demand for applied them uniformly over the whole FPGA. Experimental results show the efficiency of the proposed framework in terms of error correction, with acceptable penalties in device area and Energy×Delay Product (EDP) due to the redundant hardware resources.

Last update: 15 November 2017