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A Novel Algorithm for Temperature-Aware P&R on 3D FPGAs
 
K. Siozios, and D. Soudris
IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Oct. 2008, Rhodes, Greece
 
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Abstract:
Using new silicon technologies, increasing logic densities and clock frequencies on FPGAs lead to rapid elevation in power density. Since the power consumption is a critical challenge for designing Three Dimensional (3D) Integrated Circuits (ICs), a novel temperature-aware placement and routing (P&R) algorithm targeting to 3D FPGAs, is introduced. The proposed algorithm achieves to redistribute the switched capacitance over the hardware resources in a rather “balanced” profile, reducing the maximum value, as well as the total number of power/temperature hotspots. For evaluation purposes, the proposed approach is realized as part of an existing tool, named 3DPRO. Comparing to alternative solutions, we achieve to reduce the percentage of silicon area that operates under high power by 68%, while we also lead to average energy savings about 6%, with negligible penalty in application’s delay.

Last Update: 09 October 2016