Efficient Power Management Strategy of FPGAs Using a Novel Placement Technique
K. Siozios, D. Soudris and A. Thanailakis
IFIP International Conference on Very Large Scale Integration (VLSI-SoC), pp. 204-209, Oct. 2006, Nice, France
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Power consumption is one of the major headaches, which should be tackled by the designers. Also, the parameters that affect significantly the performance and power are the Configurable Logic Blocks (CLBs) and the interconnection components. A novel approach for efficient implementation of applications onto reconfigurable architectures is introduced. The main goal of this technique is to spread out the power consumption across the whole device, as well as to minimize it, achieving a more uniform power consumption map across the whole FPGA. This approach is based on finding the optimal CLB placement according to resource utilization map. The proposed methodology can be applied for mapping applications with an efficient power management strategy. Furthermore, the proposed placement algorithm reduces the total power consumption, the leakage power, the total energy and silicon area. The proposed methodology is fully-supported by the software tool called EX-VPR. The result of applying this placement strategy is the power consumption reduction about 5%, while we distribute the power consumption with a rather "uniformly" fashion across the whole device minimizing the power spikes.

Last Update: 09 October 2016