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The AMDREL Project in Retrospective
 
K. Siozios, G. Koutroumpezis, K. Tatas, N. Vassiliadis, V. Kalenteridis, H. Pournara, I. Pappas, D. Soudris, S. Nikolaidis, S. Siskos, and A. Thanailakis
IFIP International Conference on Very Large Scale Integration (VLSI-SoC), Oct. 2005, Australia
 
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Abstract:
The design of a novel embedded fine-grain reconfigurable hardware architecture (FPGA) is introduced. The architecture features a number of circuit-level low-power techniques, since power consumption was considered as a primary design goal. Additionally, EX-VPR and DAGGER software tools (part from the MEANDER framework) were presented. The developed tool set design flow is used for mapping logic to the FPGA platform. The novel energy-efficient FPGA architecture was implemented in 0.18μm STM CMOS technology. The efficiency of the entire system (FPGA and tools) was proven by comparisons with the existing contemporary commercial and academic FPGA systems.

Last update: 15 November 2017