A Systematic Methodology for Reliability Improvements on SoC-based Software Defined Radio Systems
D. Diamantopoulos, K. Siozios, S. Xydis and D. Soudris
VLSI Design, Vol. 2012, Article ID 784945, 15 pages
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Shrinking silicon technologies, increasing logic densities and clock frequencies, lead to a rapid elevation in power density. Increased power density results in higher on-chip temperature, which in turn creates numerous problems tightly firmed to reliability degradation. This problem is expected to become even more severe for mobile architectures, because they could not employ costly cooling techniques. Since typical low-power design has been proved inefficient to tackle the temperature increment by itself, device architects are facing the challenge of developing new methodologies to guarantee timing, power and thermal integrity of the chip. In this paper, we propose a thermal-aware exploration framework targeting to temperature hotspots elimination through the efficient exploration of multiple micro-architecture selections over the temperature-area trade-off curve. By carefully planning at design time the resources of the initial micro-architecture that should be replicated, the proposed methodology optimizes the system's thermal profile and flattens on-chip temperature under various design constraints. The introduced framework does not impose any architectural or compiler modification, whereas it is orthogonal to any other thermal-aware methodology. For evaluation purposes, we employ the Software Defined Radio executed onto a thermal-aware instance of LEON3 processor. Based on the experimental results we found that our methodology leads to an architecture that exhibits temperature reduction of 17 Kelvin degrees, which leads to improvement against aging phenomena about 14%, with a controllable overhead in silicon area about 15%, in comparison to the initial (original) LEON3 instance.

Last Update: 09 October 2016