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On Supporting Adaptive Fault Tolerant at Run-Time with Virtual FPGAs
 
K. Siozios, D. Soudris and M. Hubner
International Parallel and Distributed Processing Symposium Workshops (IPDPSW), pp. 2206–2211, May 2013, Cambridge, MA.
 
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Abstract:
For decades computer architects pursued one primary goal: performance. The even-faster transistors provided by Moore's law were translated into remarkable gains in operation frequency and power consumption. However, the device-level size and architecture complexity imposes several new challenges, including a decrease in dependability level due to physical failures. This makes crucial the usage of fault tolerance. Existing solutions are applied statically at design-time ignoring about constraints posed during execution phase, while they also introduce mentionable overheads in terms of delay and power consumption. In this paper we introduce a software-supported methodology based on game theory for adapting the aggressiveness of fault tolerance at run-time. Experimental results prove the efficiency of our methodology since it achieves comparable fault masking to relevant solutions, but with significant lower mitigation cost.

Last update: 15 November 2017