HVSoCs: A Framework for Rapid Prototyping of 3-D Hybrid Virtual System-on-Chips
D. Diamantopoulos, K. Siozios, E. Sotiriou-Xanthopoulos, G. Economakos and D. Soudris
IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), pp. 2194–2199, May 2013, Cambridge, MA.
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In embedded system domain there is a continues trend towards providing higher flexibility for application development. This imposes that the development of distinct components cannot be though as affordable for System-on-Chip platforms, whereas a more holistic approach is necessary for deriving optimal solutions. At the same time, the requirement for integrating more functionality in a smaller form factor, or the integration into single chip different technologies (e.g. memory, logic and sensors) pushes traditional semiconductor technology scaling to its limits. Three-dimensional (3-D) chip stacking is touted as the silver bullet technology that can keep Moore's momentum and fuel the next wave of consumer electronic products. Apart from this flexibility, up to now there is a lack of tools, where designers can effectively produce these new platforms. This paper introduces a new design paradigm, named Hybrid Virtual System-on-Chip, in order to support rapid evaluation of different technologies for IC product development. Our framework initiates from SystemC, whereas the target architecture consists of a 3-D chip. Rather than similar approaches which mainly are based on academic tools, the 3-D HVSoCs is evaluated with the usage of Cadence tools.

Last Update: 09 October 2016