A Customizable Framework for Application Implementation onto 3-D FPGAs
K. Siozios and D. Soudris
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 35, No. 11, pp. 1783-1796, 2016, DOI: 10.1109/TCAD.2016.2529421
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Integrating more functionality in a smaller form factor with higher performance and lower-power consumption is pushing semiconductor technology scaling to its limits. Three-dimensional (3-D) chip stacking is touted as the silver bullet technology that can keep Moore's momentum and fuel the next wave of consumer electronic products. Additionally, the complexity of digital designs imposes that CAD algorithms are getting harder and slower. This article introduces a framework for application implementation onto 3-D reconfigurable architectures. In contrast to existing approaches, the proposed solution is customizable according to constraints posed by the application and the target 3-D device in order to improve performance metrics. Experimental results highlight the effectiveness of our framework, as we achieve average enhancements in terms of maximum operation frequency and power consumption by 35% and 47%, respectively, as compared to state-of-the-art algorithms.

Last Update: 09 October 2016