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Trading Fault-Masking with Performance Overhead for FPGAs
 
K. Siozios and D. Soudris
Workshop Proceedings on International Coference on Architecture of Computing Systems (ARCS), pp. 7-10, Feb. 2011, Como, Italy
 
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Abstract:
Reliability issues become an important design concern with technology scaling. This paper introduces a novel methodology for balancing the desired fault masking and the consequence delay and power overheads due to redundancy. Experimental results shown that our solution outperforms similar approaches since it achieves average delay and power savings up to 25% and 35%, respectively, for comparable fault masking to existing commercially available solutions.

Last Update: 09 October 2016