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 Co-Design of Many-Accelerator Heterogeneous Systems Exploiting Virtual Platform
 
E. Sotiriou-Xanthopoulos, S. Xydis, K. Siozios and G. Economakos
International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), pp. 1-8, July 2014, Samos, Greece.
 
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Abstract:
Modern multiprocessor heterogeneous systems incorporating multiple hardware accelerators on chip have resulted to an excessive increase in the complexity of hardware/software co-design. Designers have now to explore a design space including both per-accelerator architectural parameters as well as also inter-accelerator combinations, i.e. different design configurations among the allocated accelerators, as each accelerator instance has different computational requirements, according to different input data, while throughput and area constraints should be met as well. Under such a system scenario, virtual platform prototyping suffers from increased design time phases, since it requires an exponentially larger number of evaluations to succeed adequate coverage of the design space. In addition, the system evaluation is a very slow task, especially in case of cycle-accurate virtual platforms. In this paper, we propose a co-design framework on top of virtual prototyping solution, customized for many-accelerator heterogeneous systems. The proposed framework defines separate configurations for each accelerator component of the virtual platform, instead of using only one common configuration, thus succeeding to meet both the area and the throughput constraints. In addition, as the design space size increases exponentially, the proposed framework utilizes process-based reconfigurable SystemC modules to intelligently bypass the non-productive simulation stages, thus delivering faster hardware/software co-design cycles. A case study emulating an heterogeneous server system for simultaneous video decoding of multiple streams shows the efficiency of the proposed approach, delivering design solutions with up to 1.58x improved area or 1.59x improved throughput, while achieving simulation time gains of 40%.

Last update: 15 November 2017