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An Efficient Approach for Managing Power Consumption Hotspots Distribution on 3D FPGAs
 
K. Siozios, and D. Soudris
International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), pp. 439-448, Sep. 2008, Lisbon, Portugal
 
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Abstract:
Using new silicon technologies, increasing logic densities and clock frequencies on FPGAs lead to rapid elevation in power density. Since the power consumption is a critical challenge for application implementation, a novel power-aware partitioning, placement and routing (P&R) algorithm targeting to 3D FPGAs, is introduced. The proposed methodology achieves to redistribute the switched capacitance over the hardware resources in a rather "balanced" profile, reducing among others the maximal on-chip temperatures. Due to the relation between switched capacitance and power consumption, the proposed P&R algorithm can be considered as a power management approach. This algorithm is realized as part of 3DPRO tool. Comparing to alternative P&R solutions, we eliminate the area on hotspots about 68%, while we achieve savings in delay and energy consumption about 9% and 11% in average, respectively.

Last update: 15 November 2017