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A Framework for Supporting Parallel Application Placement onto Reconfigurable Platforms
 
D. Diamantopoulos, K. Siozios, S. Xydis and D. Soudris
Workshop on Parallel Programming and Run-time Management Techniques for Many-core Architectures, Jan. 2013, Berlin, Germany.
 
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Abstract:
Placement is an essential step in Electronic Design Automation (EDA). An inferior placement will not only affect the performance of digital applications mapped onto the FPGA, but might also make the circuit unroutable by producing excessive wirelength, which is beyond the available fabricated routing resources. Throughout this paper we propose a novel placer, based on genetic algorithm, targeting to FPGAs. Rather than relevant approaches which are executed sequentially, the new placer exhibits inherent parallelism, which can be benefit from multi-core processors. Experimental results prove the effectiveness of this solution, since it reduces significantly the execution run-time (on average by 6.3x), whereas it leads also to average increase in maximum operating frequency by 12%.

Last Update: 09 October 2016