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A Framework for Rapid Evaluation of Heterogeneous 3-D NoC Architectures
 
E. Sotiriou-Xanthopoulos, D. Diamantopoulos, K. Siozios, G. Economakos and D. Soudris
Microprocessors and Microsystems, Vol. 38, pp.292-303, 2014
 
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Abstract:
The scalability of communication infrastructure in modern Integrated Circuits (ICs) becomes a challenging issue, which might be a significant bottleneck if not carefully addressed. Towards this direction, the usage of Networks-on-Chip (NoC) is a preferred solution. In this work, we propose a software-supported framework for quantifying the efficiency of heterogeneous 3-D NoC architectures. In contrast to existing approaches for NoC design, the introduced heterogeneous architecture consists of a mixture of 2-D and 3-D routers, which reduces the delay and power consumption with a slight impact on packet hops. More specifically, the experimental results with a number of DSP applications show the effectiveness of the introduced methodology, as we achieve on average 25% higher maximum operation frequency and 39% lower power consumption compared to the uniform 3-D NoCs.

Last update: 15 November 2017