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A Methodology for Alleviating the Performance Degradation of TMR Solutions
 
K. Siozios and D. Soudris
IEEE Embedded Systems Letters, Vol. 2, No. 4, pp. 111-114, Dec. 2010
 
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Abstract:
The shrinking of process technologies in conjunction to the manufacturing and transient faults may be abundant in high density reconfigurable architectures. Design of reliable applications on such unreliable architectures requires techniques able to provide a balance between the desired fault masking and the associated performance and power degradation. Starting from a well established solution for reliability improvement in field-programmable gate arrays (FPGAs) domain, we discuss a software-supported methodology that removes redundancy as much as possible from the design without affecting it’s efficiency in terms of fault masking. Based on experimental results, our proposed methodology achieves comparable fault masking with commercial solutions, but in reasonable lower mitigation cost.

Last Update: 09 October 2016