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A low-cost fault tolerant solution targeting commercial FPGA devices
 
K. Siozios and D. Soudris
Journal of System Architecture (JSA), Vol. 59, pp. 1255-1265, 2013.
 
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Abstract:
Technology scaling, in conjunction to the trend towards higher operation frequency, results in increased thermal stress, which in turn leads to upsets due to reliability degradation. In this paper, we introduce a software-supported framework targeting to enable sufficient fault coverage against upsets occurred due to aging phenomena. Experimental results with a number of industrial oriented DSP kernels shown the effectiveness of our framework, since we achieved average improvement in terms of maximum operation frequency and power consumption by 15% and 70%, respectively, as compared to a well-established commercial solution, for comparable fault masking.

Last update: 15 November 2017