A Novel Allocation Methodology for Partial and Dynamic Bitstream Generation of FPGA Architectures
K. Siozios, D. Soudris, and A. Thanailakis
Journal of Circuits, Systems, and Computers (JCSC), Vol. 19, No. 3, pp. 701-717, May 2010.
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Partially- and dynamically-reconfigurable FPGA systems offer the service of modifying part of their functionalities only when needed, while the remaining part of the FPGA device continues its execution. This paper proposes a novel allocation methodology for realizing applications with partial and dynamic features on FPGAs. It consists of two stages: the first one modifies the configuration data of each partial bitstream by re-placing the associated logic modules (or slices), having as goal to compact the slices distribution, while keeping the same functionality. The second one determines the appropriate spatial location in the FPGA device where the previously-optimized configuration data should be placed. The proposed manager is device independent, since it derives partial configuration data that can program dynamically any island-style or hierarchical FPGA, while it can also be used to re-allocate (or defrag) a reconfigurable architecture. For demonstration purposes we implemented the allocation methodology into a bitstream generator tool, named DAGGER (part from the MEANDER framework) targeting to Virtex-like architectures.

Last Update: 09 October 2016