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A High-Level Mapping Algorithm Targeting to 3D NoC Architectures with Multiple Vdd
 
K. Siozios, I. Anagnostopoulos and D. Soudris
IEEE Annual Computer Symposium on VLSI (ISVLSI), pp. 444-445, July 2010, Kefalonia, Greece.
 
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Abstract:
The communication problem in modern ICs becomes a challenge issue. This paper introduces a high-level mapping algorithm targeting to low-power 3D NoC devices. By appropriately assigning application’s functionalities to layers with different supply voltages we achieve reasonable energy savings and temperature reduction. Additionally, our methodology supports real-time adaption on different traffic scenarios. Experimental results show that energy savings up to 19% are feasible, without any area and delay overhead, as compared to architectures powered by only one supply voltage.

Last update: 15 November 2017