Dr. Kostas Siozios @ Internet


K. Siozios, D. Soudris and A. Thanailakis, "A Novel Methodology for Designing High-Performance and Low-Power FPGA Interconnection Targeting DSP Applications", International Symposium on Circuits and Systems (ISCAS), pp. 4383-4386, Kos, Greece, 2006
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The novel design of an efficient FPGA interconnection architecture with multiple Switch Boxes (SB) and hardwired connections for realizing data intensive applications (i.e. DSP applications), is introduced. For that purpose, after exhaustive exploration, we modify the routing architecture through efficient selection of the appropriate switch box with hardwired connections, taking into account the statistical and spatial routing restrictions of DSP applications mapped onto FPGA. More specifically, we propose a new technique for selecting the appropriate combination of switch boxes, depending on the localized performance and power consumption requirements of each specific region of FPGA architecture. In order to perform the mapping, we developed a novel algorithm, which takes into account the modified architectural routing features. This algorithm was implemented within a new tool called EX-VPR. Using a number of DSP applications, extensive comparison study of various combinations of switch boxes in terms of total power consumption, performance, Power×Delay product prove the effectiveness of the proposed approach.

Last update: 18 May 2018