HOME PUBLICATIONS EDUCATION RESEARCH PROJECTS SOFTWARE FUNNY CONTACT

A Novel Prototyping and Evaluation Framework for NoC-based MPSoC
 
K. Tatas, K. Siozios, A. Bartzas, C. Kyriacou and D. Soudris
International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS), Vol. 4, No. 3, pp. 1-24, 2013.
 
   Download Paper [BibTeX] [EndNote] [Plain]
Abstract:
This paper presents a framework for high-level exploration, Register Transfer-Level (RTL) design and rapid prototyping of Network-on-Chip (NoC) architectures. From the high-level exploration, a selected NoC topology is derived, which is then implemented in RTL using an automated design flow. Furthermore, for verification purposes, appropriate self-checking testbenches for the verification of the RTL and architecture files for the semi-automatic implementation of the system in Xilinx EDK are also generated, significantly reducing design and verification time, and therefore Non-Recurring Engineering (NRE) cost. Simulation and FPGA implementation results are given for four case studies multimedia applications, proving the validity of the proposed approach.

Last update: 15 November 2017