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Framework for Performing Rapid Evaluation of 3-D SoCs
 
D. Diamantopoulos, K. Siozios and D. Soudris
IET Electronic Letters, pp. 679-681, June 2012.
 
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Abstract:
Integrating more functionality in a smaller form factor with lower power consumption pushes traditional semiconductor technology scaling to its limits. Three-dimensional (3D) chip stacking is touted as the silver bullet technology that can keep Moore’s momentum and fuel the next wave of consumer electronic products. Introduced is a framework that enables rapid evaluation of 3D SoCs with existing physical design tools.

Last update: 15 November 2017