Architecture-Level Exploration of Alternative Interconnection Schemes Targeting 3D FPGAs: A Software-Supported Methodology
K. Siozios A. Bartzas and D. Soudris
International Journal of Reconfigurable Computing, Vol. 2008, Article ID 76942, 18 pages.
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In current reconfigurable architectures the interconnection structures increasingly contribute more to the delay and power consumption. The demand for increased clock frequencies and logic density (smaller area footprint) makes the problem even more important. Three-dimensional (3D) architectures are able to alleviate this problem by accommodating a number of functional layers, each of which might be fabricated in different technology. However, the benefits of such an integration technology have not been sufficiently explored yet. In this paper we propose a software-supported methodology for exploring and evaluating alternative interconnection schemes for 3D FPGAs. In order to support the proposed methodology, three new CAD tools were developed: (i) a tool that partitions the application to the available functional layers of the 3D architecture, (ii) a placement and routing tool for 3D FPGA with full-custom interconnection fabric and (iii) a tool for estimating the power/energy consumption for such architectures. These three tools are part of the 3D MEANDER Design Framework. During our exploration we study the impact of vertical interconnection between functional layers in a number of design parameters. More specifically, the average gains in operation frequency; power consumption and wirelength are 35%, 32% and 13%, respectively, compared to existing 2D FPGAs with identical logic resources. Also, we achieve higher utilization ratio for the vertical interconnections compared to existing approaches by 8% for designing 3D FPGAs, leading to cheaper and more reliable devices.

Last Update: 09 October 2016