HOME PUBLICATIONS EDUCATION RESEARCH PROJECTS SOFTWARE FUNNY CONTACT

A Methodology and Tool Framework for Supporting Rapid Exploration of Memory Hierarchies in FPGAs
 
H. Sidiropoulos, K. Siozios and D. Soudris
International Conference on Field Programmable Logic and Applications, pp. 238-243, Sept. 2011, Chania, Greece
 
   Download Paper [BibTeX] [EndNote] [Plain]
Abstract:
This paper introduces a novel methodology for enabling rapid exploration of memory hierarchies onto FPGA devices. The methodology is software supported by a new open-source tool framework, named NAROUTO. Among others, the proposed framework enables critical tasks during architecture’s design, such as memory hierarchy and floorplanning. Furthermore, NAROUTO framework is the only available solution for power/energy evaluation of different memory organizations. Experimental results shown that NAROUTO framework leads to significant area, power (about 82%) and performance (about 46%) improvements, as compared to existing solutions.

Last Update: 09 October 2016