Dr. Kostas Siozios @ Internet

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H. Sidiropoulos, K. Siozios and D. Soudris, "A Framework for Architecture-level Exploration of Communication Intensive Applications onto 3-D FPGAs", International Conference on Field Programmable Logic and Applications (FPL), pp. 30-33, Sept. 2011, Chania, Greece.
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Abstract:
Interconnection structures in FPGAs increasingly contribute more to the delay and power consumption. Three-dimensional (3-D) chip stacking is touted as the silver bullet technology that can keep Moore’s momentum and fuel the next wave of consumer electronics products. However, the benefits of such a technology have not been sufficiently explored yet. This paper introduces a novel 3-D FPGA, where logic, memory and I/O resources are assigned to different layers. Experimental results prove the efficiency of our architecture for a wide range of application domains, since we achieve average performance improvement and power saving of 30% and 10%, respectively.
 

Last update: 18 May 2018