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Designing 2D and 3D Network-on-Chip Architectures
 
Editors: K. Tatas, K. Siozios, A. Jantsch and D. Soudris, Springer, 2014.
 
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Abstract:
As information technology progresses at unhampered speed, computing devices become more powerful, smaller, cheaper and pervasive in everyday’s life. A recent trend in technology development leads to quickly growing number of cores in each processing chip and soon we will routinely buy computers and other electronic gadgets with 10s and 100s of cores. This rapid growth in number of cores and parallelism requires efficient interconnection among the processing cores in terms of performance, cost and power efficiently if the processing power is to be utilized effectively. This book is at the same time a textbook that provides basic concepts, essential knowledge and course exercises as well as a current snapshot of industrial and academic research in the area of Network-on-Chip interconnect. It underlines the design challenges and shows the evolution of NoC technology, in its every facet: architectures, algorithms, tools etc.

Last update: 15 November 2017