Amdrel: A Novel Low-Energy FPGA Architecture and Supporting CAD Tool Design Flow
D. Soudris, K. Tatas, K. Siozios, G. Koutroumpezis, S. Nikolaidis, S. Siskos, N. Vasiliadis, V. Kalenteridis, H. Pournara and I. Pappas
Chapter 3 in "Fine- and Coarse-Grain Reconfigurable Systems", Editors: S. Vassiliadis and D. Soudris, Springer, 2007, pp. 152-180
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This chapter describes a complete system for the implementation of digital logic in a fine-grain reconfigurable platform (FPGA). The energy-efficient FPGA architecture is designed and simulated in STM 0.18μm CMOS technology. The detailed design and circuit characteristics of the Configurable Logic Block and the interconnection network are determined and evaluated in terms of energy, delay and area. A number of circuit-level low-power techniques are employed because power consumption is the primary concern. Additionally, a complete tool framework for the implementation of digital logic circuits in FPGA platforms is introduced. The framework is composed of i) nonmodified academic tools, ii) modified academic tools and iii) new tools. The developed tool framework supports a variety of FPGA architectures. Qualitative and quantitative comparisons with existing academic and commercial architectures and tools are provided, yielding promising results.

Last update: 15 November 2017