Dr. Kostas Siozios @ Internet


D. Soudris, K. Tatas, K. Siozios, G. Koutroumpezis, S. Nikolaidis, S. Siskos, N. Vasiliadis, V. Kalenteridis, H. Pournara and I. Pappas, "Amdrel: A Novel Low-Energy FPGA Architecture and Supporting CAD Tool Design Flow ", Chapter in "Fine- and Coarse-Grain Reconfigurable Systems", Editors: S. Vassiliadis and D. Soudris, Springer, pp. 152-180, 2007.
[BibTeX] [EndNote] [Plain]
Download Paper
This chapter describes a complete system for the implementation of digital logic in a fine-grain reconfigurable platform (FPGA). The energy-efficient FPGA architecture is designed and simulated in STM 0.18μm CMOS technology. The detailed design and circuit characteristics of the Configurable Logic Block and the interconnection network are determined and evaluated in terms of energy, delay and area. A number of circuit-level low-power techniques are employed because power consumption is the primary concern. Additionally, a complete tool framework for the implementation of digital logic circuits in FPGA platforms is introduced. The framework is composed of i) nonmodified academic tools, ii) modified academic tools and iii) new tools. The developed tool framework supports a variety of FPGA architectures. Qualitative and quantitative comparisons with existing academic and commercial architectures and tools are provided, yielding promising results.

Last update: 18 May 2018