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A Novel NoC Architecture Framework for 3D Chip MPSoC Implementations
 
K. Tatas, C. Kyriacou, A. Bartzas, K. Siozios and D. Soudris
Friday Workshop on 3D Integration at Design, Automation and Testing in Europe (DATE), 24 April 2010, Germany.
 
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Abstract:
This paper presents a framework for high-level exploration and RTL design of an optimized Network-on-Chip (NoC) architecture for 3D chips. The RTL is derived from the high-level exploration methodology in a semi-automated way. FPGA implementation figures are given for various implementation parameters of the Network Interface Element, demonstrating the performance/area trade-off of 3D NoC architectures. Additionally, power consumption measurements for 2D and 3D Network Interface Elements are provided for FPGA prototype implementation.

Last Update: 09 October 2016