Topology Exploration and Buffer Sizing for Three-Dimensional Networks-on-Chip
A. Bartzas, K. Siozios, and D. Soudris
Friday Workshop on 3D Integration at Design, Automation and Testing in Europe (DATE)
, Friday 24 April 2009, Nice, France.
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In this work we present an exploration methodology designing alternative 3D NoC architectures. We define as 3D NoCs these architectures composed of many layers, where each layer is a two-dimensional NoC grid, where the grids are the same for all the layers, composed of elements of the same type(s). The main objective of the methodology is to derive to heterogeneous 3D NoC topologies with a mix of 2D and 3D routers and vertical link interconnection patterns that perform best to the incoming traffic. Furthermore, the combination of priority-based QoS and buffer sizing techniques is proposed for the first time. The starting point of the proposed methodology is an already optimized mapping [7] which is 32% better than other solutions. In this way additional improvements in latency and energy consumption can be achieved. Moreover, the proposed methodology is applied in computationally intensive applications, e.g. DSP, mapped into 2D and 3D NoC mesh architectures. The cost factors we consider are: a) energy consumption; b) average packet latency and c) total switch block area.

Last Update: 09 October 2016