Architectures and CAD Tools for 3D FPGAs
K. Siozios, H. Sidiropoulos and D. Soudris
Book Chapter in "Reconfigurable Logic: Architecture, Tools and Applications", pp. 489-511, CRC press, Oct. 2015.
   Download Paper [BibTeX] [EndNote] [Plain]
Field-Programmable Gate Arrays (FPGAs) have become the implementation medium for the majority of digital circuits. The key to FPGAs’ popularity is their feature to support application implementation by appropriately (re-)configuring the functionality of hardware resources. This allows FPGAs to provide higher flexibility, rapid product prototyping and significantly reduced non-recurring engineering (NRE) costs, as compared to ASIC (Application-Specific Integrated Circuit) devices. Additionally, this situation makes the FPGA paradigm to grow in importance, as there is a stronger demand for faster, smaller, cheaper, and lower-energy devices.

For decades, semiconductor manufacturers have been shrinking transistor size in Integrated Circuits (ICs) to achieve the yearly increases in performance described by Moore’s Law, which exists only because the RC delay was negligible, as compared to the signal propagation delay. For sub-micron technology, however, the RC delay becomes a dominant factor. Furthermore, previous studies showed that at 130nm technology node approximately 51% of the microprocessor’s power is consumed by interconnect fabric. This has generated many discussions concerning the end of device scaling as we know it, and has hastened the search for solutions beyond the perceived limits of current 2-D devices.

Three dimensional (3-D) chip stacking is considered by many as the silver bullet technology that will accommodate for all the aforementioned requirements. Stacking multiple dies in the vertical axis and interconnecting them using very fine-pitch Through Silicon Vias (TSVs) enables the creation of chips with very diverse functionalities implemented in different process technologies in a very small form factor. Introducing locality along the z-axis enables on average shorter interconnections between system components, which in turn leads to reduced signal propagation delay compared to conventional (i.e. 2-D) architectures. Additionally, by stacking smaller die rather than manufacturing a large planar die also leads to yield, hence cost, improvement because the probability that a die is defective is positively correlated with its area. Consequently, the shift from horizontal to vertical stacking of circuits has the potential to rewrite the conventions of electronics design.

The benefits of using 3-D integration in logic chips are especially great for designing FPGAs, as compared to other ICs, since these architectures suffer from data communication problems; interconnection delay and power/energy consumption are the main bottlenecks compared to alternative ASIC implementations. Hence, it is likely that the reconfigurable architectures will drive rapid adoption of 3-D integration, faster than any other device. However, in order such a technology to be widely accepted, several challenges need to be satisfied. For instance, methodologies, algorithms and tools that facilitate the architecture-level exploration, as well as the application mapping onto 3-D platforms are essential.

This chapter summarizes a number of approaches related to the 3-D reconfigurable domain. Towards this direction, both architectural and algorithmic solutions are discussed.

Last Update: 09 October 2016