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Three Dimensional Network-on-Chip Architectures
 
A. Bartzas, K. Siozios, and D. Soudris
Book Chapter "Networks on Chips: Theory and practice", Editors: F. Gebali, H. Elmiligi, M. W. El-Kharashi, pp. 1–28, CRC Press, 2008.
 
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Abstract:
Future integrated systems will contain billion of transistors [51], composing tens to hundreds of IP cores. These IP cores, implementing emerging complex multimedia and network applications, should be able to deliver rich multimedia and networking services. An efficient cooperation among these IP cores (e.g., e cient data transfers) can be achieved through utilization of the available resources.

The design of such complex systems includes several challenges to be addressed. Among others one challenge is to design an on-chip interconnection network that should be able to e ciently connect the IP cores. Another challenge is to derive such an application mapping that will make e cient usage of the available hardware resources [39, 21]. An architecture that is able to accommodate such a high number of cores, satisfying the need for communication and data transfers, is the Network-on-Chip (NoC) architecture [5, 25]. For these reasons Networks-on-Chip become a popular choice for designing the on-chip interconnect for Systems-on-Chip (MPSoCs), and are supported from the industry (such as the AEthereal NoC from Philips, the STNoC from STMicroelectronics and an 80-core NoC from Intel). As it is presented in [43], the key design challenges of emerging NoC design are a) the communication infrastructure, b) the communication paradigm selection and c) the application mapping optimization.

The type of the IP cores (their characteristics, capabilities) as well as the topology and interconnection scheme plays an important role on how e ciently an NoC will perform for a certain application or set of applications. Furthermore, the application features (e.g., data transfers, communication and computation needs) plays an equally important role in the overall performance of the NoC system. For this reason, in order to take full advantage of the hardware resources the NoC architecture should be able to accommodate e ciently the applications' needs providing an application-speci c (an application-domain specific) architecture. An overview of the cost considerations on the design of NoCs is given at [9]. Up to now NoC designs were limited to two dimensions. But the currently emerging 3D integration technology exhibits, among others, two major advantages, namely higher performance and smaller energy consumption. A survey of existing 3D fabrication technologies is presented in [8], showing the available interconnection architectures among the layers of 3D integrated circuits and illustrating the main research issues in current and future 3D technologies. So, due to process / integration technology advancements, it is feasible to design and manufacture NoCs that will expand to the third dimension (3D NoCs). In order to satisfy the demands of emerging systems for scaling, performance and functionality 3D integration is a way to accommodate these demands. For example, a considerable reduction can be achieved in the number and length of global interconnect using three-dimensional integration.

In this chapter we present an architectural exploration methodology designing alternative 3D NoC architectures. We de ne as 3D NoCs these architectures composed of many layers, where each layer is a two-dimensional NoC grid, where the grids are the same for all the layers, composed of elements of the same types. The main objective of the methodology is to derive to heterogeneous 3D NoC topologies with a mix of 2D and 3D routers and vertical link interconnection patterns that performs best to the incoming tra c. The cost factors we consider are: (i) energy consumption; (ii) average packet latency and (iii) total switch block area, and we perform comparisons against an NoC that all the routers are 3D ones. We have employed and extended the Worm Sim NoC simulator, being able to model these heterogeneous architectures and simulate them, gathering information on how they perform. The NoC heterogeneity can be achieved using a mix of two- and three-dimensional routers for each layer of the NoC, which implies to a "reduced" presence of vertical interconnection links. The design methodology evaluates such heterogeneous topologies, targeting mesh and torus ones, for various inputs and shown which ones can handle best the corresponding types of trafic
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Last update: 15 November 2017