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AMDREL: A Novel Low-Energy FPGA Architecture and Supporting CAD Tool Design Flow
 
D. Soudris, S. Nikolaidis, S. Siskos, K. Tatas, K. Siozios, G. Koutroumpezis, N. Vasiliadis, V. Kalenteridis, H. Pournara, I. Pappas, and A. Thanailakis
Proceedings of ASP-DAC 2005, Asia South Pacific Design Automation Conference (Design Contest), pp. D3-D4, 2005, Shanghai, China
 
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Abstract:
The design of a novel embedded FPGA reconfigurable hardware architecture is introduced. The architecture features a number of circuit-level low-power techniques, since power consumption is considered a primary concern. Additionally, a complete set of tools facilitating implementation of applications on the proposed FPGA was presented, starting from an RTL description and producing the actual configuration bit stream. The designed full-custom FPGA is under fabrication in 0.18μm STM CMOS technology. The prototype supports partial and dynamic reconfiguration. The efficiency of the entire system (FPGA and tools) was proven by comparisons with commercial systems.

Last Update: 09 October 2016