Fast Design Space Exploration Environment Applied on NoC's for 3D-Stacked MPSoC's
A. Richard, D. Milojevic, F. Robert, A. Bartzas, A. Papanikolaou, K. Siozios and D. Soudris
International Conference on Architecture of Computing Systems (ARCS), pp. 1–6, Hannover, Germany, Feb. 2010.
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In this paper we present a design methodology and associated tool chain for efficient design of complex MPSoC architectures implemented using 3D-Stacked Integrated Circuits (3D-SIC). The proposed framework is based on a three step methodology that combines relatively accurate high-level, and two more accurate low-level prototyping tools. The highlevel exploration tool, Nessie, developped at the ULB, allows designers to quickly simulate several system architecture and application scenarios. Using Nessie, the designer can easily explore many different system level options before deciding on the design space points he would like to explore in more details. In this paper, the high-level estimations are subsequently validated using an existing C++, transaction-level, 3D-SIC aware NoC simulator. Then, floorplaning and global routing of the system are performed using a novel tool for 3D physical prototyping. The low-level performance metrics of the system are derived from the resulting physical prototype and can be compared to the results predicted by Nessie. We demonstrate our approach using the example of a fairly complex MPSoC platform dedicated to advanced high-performance and low power video coding applications (AVC/H.264 encoder). The MPSoC platform is prototyped as traditional 2D-IC and then as 3D-SIC design using various 3D stack configurations and stack assignment schemes.

Last Update: 09 October 2016