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Parameter Sensitivity in Virtual FPGA Architectures
 
P. Figuli, W. Ding, S. Figuli, K. Siozios, D. Soudris, and J. Becker
International Workshop on Applied Reconfigurable Computing (ARC), Netherlands, April 3 - 7, 2017, (accepted for publication)
 
   The paper will be available after publication [BibTex] [EndNote] [Plain]
Abstract:
Virtual FPGAs add the benefits of increased exibility and application portability on bitstream level across any underlying commercial of-the-shelf FPGAs at the expense of additional area and delay overhead. Hence it becomes a priority to tune the architecture parameters of the virtual layer. Thereby, the adoption of parameter recommendations intended for physical FPGAs can be misleading, as they are based on transistor level models. This paper presents an extensive study of architectural parameters and their e ects on area and performance by introducing an extended parameterizable virtual FPGA architecture and deriving suitable area and delay models. Furthermore, a design space exploration methodology based on these models is carried out. An analysis of over 1400 benchmark-runs with various combinations of cluster and LUT size reveals high parameter sensitivity with variances up to 23:6% in area and 19:0% in performance and a discrepancy to the studies on physical FPGAs.

Last Update: 19 January 2017