Dynamic Memory Management in Vivado-HLS for Scalable Many-Accelerator Architectures
D. Diamantopolous, S. Xydis, K. Siozios and D. Soudris
 Workshop on Applied Reconfigurable Computing (ARC), pp. 117-128, April 2015, Bochum, Germany.
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This paper discusses the incorporation of dynamic memory management during High-Level-Synthesis (HLS) for effective resource utilization in many-accelerator architectures targeting to FPGA devices. We show that in today's FPGA devices, the main limiting factor of scaling the number of accelerators is the starvation of the available on-chip memory. For many-accelerator architectures, this leads in severe inefficiencies, i.e. memory-induced resource under-utilization of the rest of the FPGA's resources. Recognizing that static memory allocation - the de-facto mechanism supported by modern design techniques and synthesis tools - forms the main source of "resource under-utilization" problems, we introduce the DMM-HLS framework that extends conventional HLS with dynamic memory allocation/deallocation mechanisms to be incorporated during many-accelerator synthesis. The proposed DMM-HLS framework enables each accelerator to dynamically adapt its allocated memory according to the runtime memory requirements, thus maximizing the the overall accelerator count through effective sharing of FPGA's memories resources. We integrated the proposed framework with the industrial strength Vivado-HLS tool, and we evaluate its effectiveness with a set of key accelerators from emerging application domains. DMM-HLS delivers significant increase in FPGA's accelerators density (3.8x more accelerators) in exchange for affordable overheads in terms of delay and resource count.

Last Update: 09 October 2016